1. Technical Field
The present inventin relates to a TTL to CMOS input buffer and, more particularly, to a TTL to CMOS input buffer wherein a transition detector and an additional pair of MOS devices are included in the circuit to prevent current flow through the buffer circuit.
2. Description of the Prior Art
For many applications, it is desirable to provide a circuit which is capable of interfacing between transistor-transistor logic (TTL) levels and complementary MOS (CMOS) logic levels. In particular, TTL logic levels are nominally +2.4 V for a logic "1" and 0.4 V for a logic "0", and the associated CMOS levels are nominally +5.0 V and 0.0 V. The conventional interface circuit, also referred to in the art as an "input buffer circuit", comprises a p-channel MOS transistor and an n-channel MOS transistor connected in series between a positive power supply VDD (usually 5 V) and ground. The gates of the devices are connected together and responsive to the TTL input signal. The drains of the transistors are also connected together and provide the CMOS output signal. This arrangement is considered in the art as a typical CMOS inverter circuit. In the ideal situation, one transistor of the pair will always be "off", preventing any current to flow through the pair of transistors from VDD to ground. However, this is not always the case. In particular, problems arise at the TTL input level for a logic "1", 2.4 V, and when the TTL input level for a logic "0" is somewhat greater than 0.4 V, for example, 0.8 V. At these levels, the both transistors may be "on" and a current will flow through the transistor pair to ground.
There are many arrangements which exist in the prior art to solve this problem. One particular solution is disclosed in U.S. Pat. No. 4,471,242 issued to G. E. Noufer et al on Sept. 11, 1984. The current flow through the devices is eliminated in this arrangement by introducing a reference voltage to match the lowest level of a logic "1" of the TTL input signal. This reference voltage is utilized in place of VDD as the supply voltage to the p-channel transistor, thus preventing the p-channel transistor from turning "on" when its gate voltage is at the lowest TTL logic "1" input level. A problem with this arrangement, however, is that by reducing the supply voltage of the p-channel transistor, the operating range of the buffer circuit is also restricted. By lowering the voltage available to operate the transistors, therefore, the device will be inherently slower. For many applications, this is not acceptable.
As an alternative solution, the actual sizes of the p- and n-channel transistors may be modified to prevent the static current flow. However, this solution is not practical since it requires additional masking levels and, therefore, additional processing time. Further, it is difficult with this method to accurately control the device sizes so as to reproducibly provide the necessary threshold voltage.
Therefore, a need remains in the prior art for a TTL to CMOS input buffer which will not draw any static current, does not require additional processing steps, and is capable of operating over the entire 0-5 V CMOS power supply level.